#ifndef INCLUDED_CYFITTERIAR_INC
#define INCLUDED_CYFITTERIAR_INC
    INCLUDE cydeviceiar_trm.inc

/* BLE_bless_isr */
BLE_bless_isr__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
BLE_bless_isr__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
BLE_bless_isr__INTC_MASK EQU 0x1000
BLE_bless_isr__INTC_NUMBER EQU 12
BLE_bless_isr__INTC_PRIOR_MASK EQU 0xC0
BLE_bless_isr__INTC_PRIOR_NUM EQU 3
BLE_bless_isr__INTC_PRIOR_REG EQU CYREG_CM0_IPR3
BLE_bless_isr__INTC_SET_EN_REG EQU CYREG_CM0_ISER
BLE_bless_isr__INTC_SET_PD_REG EQU CYREG_CM0_ISPR

/* BLE_cy_m0s8_ble */
BLE_cy_m0s8_ble__ADC_BUMP1 EQU CYREG_BLE_BLERD_ADC_BUMP1
BLE_cy_m0s8_ble__ADC_BUMP2 EQU CYREG_BLE_BLERD_ADC_BUMP2
BLE_cy_m0s8_ble__ADV_CH_TX_POWER EQU CYREG_BLE_BLELL_ADV_CH_TX_POWER
BLE_cy_m0s8_ble__ADV_CONFIG EQU CYREG_BLE_BLELL_ADV_CONFIG
BLE_cy_m0s8_ble__ADV_INTERVAL_TIMEOUT EQU CYREG_BLE_BLELL_ADV_INTERVAL_TIMEOUT
BLE_cy_m0s8_ble__ADV_INTR EQU CYREG_BLE_BLELL_ADV_INTR
BLE_cy_m0s8_ble__ADV_NEXT_INSTANT EQU CYREG_BLE_BLELL_ADV_NEXT_INSTANT
BLE_cy_m0s8_ble__ADV_PARAMS EQU CYREG_BLE_BLELL_ADV_PARAMS
BLE_cy_m0s8_ble__ADV_SCN_RSP_TX_FIFO EQU CYREG_BLE_BLELL_ADV_SCN_RSP_TX_FIFO
BLE_cy_m0s8_ble__ADV_TX_DATA_FIFO EQU CYREG_BLE_BLELL_ADV_TX_DATA_FIFO
BLE_cy_m0s8_ble__AGC EQU CYREG_BLE_BLERD_AGC
BLE_cy_m0s8_ble__BALUN EQU CYREG_BLE_BLERD_BALUN
BLE_cy_m0s8_ble__BB_BUMP1 EQU CYREG_BLE_BLERD_BB_BUMP1
BLE_cy_m0s8_ble__BB_BUMP2 EQU CYREG_BLE_BLERD_BB_BUMP2
BLE_cy_m0s8_ble__BB_XO EQU CYREG_BLE_BLERD_BB_XO
BLE_cy_m0s8_ble__BB_XO_CAPTRIM EQU CYREG_BLE_BLERD_BB_XO_CAPTRIM
BLE_cy_m0s8_ble__CE_CNFG_STS_REGISTER EQU CYREG_BLE_BLELL_CE_CNFG_STS_REGISTER
BLE_cy_m0s8_ble__CE_LENGTH EQU CYREG_BLE_BLELL_CE_LENGTH
BLE_cy_m0s8_ble__CFG_1_FCAL EQU CYREG_BLE_BLERD_CFG_1_FCAL
BLE_cy_m0s8_ble__CFG_2_FCAL EQU CYREG_BLE_BLERD_CFG_2_FCAL
BLE_cy_m0s8_ble__CFG_3_FCAL EQU CYREG_BLE_BLERD_CFG_3_FCAL
BLE_cy_m0s8_ble__CFG_4_FCAL EQU CYREG_BLE_BLERD_CFG_4_FCAL
BLE_cy_m0s8_ble__CFG_5_FCAL EQU CYREG_BLE_BLERD_CFG_5_FCAL
BLE_cy_m0s8_ble__CFG_6_FCAL EQU CYREG_BLE_BLERD_CFG_6_FCAL
BLE_cy_m0s8_ble__CFG1 EQU CYREG_BLE_BLERD_CFG1
BLE_cy_m0s8_ble__CFG2 EQU CYREG_BLE_BLERD_CFG2
BLE_cy_m0s8_ble__CFGCTRL EQU CYREG_BLE_BLERD_CFGCTRL
BLE_cy_m0s8_ble__CLOCK_CONFIG EQU CYREG_BLE_BLELL_CLOCK_CONFIG
BLE_cy_m0s8_ble__COMMAND_REGISTER EQU CYREG_BLE_BLELL_COMMAND_REGISTER
BLE_cy_m0s8_ble__CONN_CE_COUNTER EQU CYREG_BLE_BLELL_CONN_CE_COUNTER
BLE_cy_m0s8_ble__CONN_CE_INSTANT EQU CYREG_BLE_BLELL_CONN_CE_INSTANT
BLE_cy_m0s8_ble__CONN_CH_TX_POWER EQU CYREG_BLE_BLELL_CONN_CH_TX_POWER
BLE_cy_m0s8_ble__CONN_CONFIG EQU CYREG_BLE_BLELL_CONN_CONFIG
BLE_cy_m0s8_ble__CONN_INDEX EQU CYREG_BLE_BLELL_CONN_INDEX
BLE_cy_m0s8_ble__CONN_INTERVAL EQU CYREG_BLE_BLELL_CONN_INTERVAL
BLE_cy_m0s8_ble__CONN_INTR EQU CYREG_BLE_BLELL_CONN_INTR
BLE_cy_m0s8_ble__CONN_INTR_MASK EQU CYREG_BLE_BLELL_CONN_INTR_MASK
BLE_cy_m0s8_ble__CONN_PARAM1 EQU CYREG_BLE_BLELL_CONN_PARAM1
BLE_cy_m0s8_ble__CONN_PARAM2 EQU CYREG_BLE_BLELL_CONN_PARAM2
BLE_cy_m0s8_ble__CONN_REQ_WORD0 EQU CYREG_BLE_BLELL_CONN_REQ_WORD0
BLE_cy_m0s8_ble__CONN_REQ_WORD1 EQU CYREG_BLE_BLELL_CONN_REQ_WORD1
BLE_cy_m0s8_ble__CONN_REQ_WORD10 EQU CYREG_BLE_BLELL_CONN_REQ_WORD10
BLE_cy_m0s8_ble__CONN_REQ_WORD11 EQU CYREG_BLE_BLELL_CONN_REQ_WORD11
BLE_cy_m0s8_ble__CONN_REQ_WORD2 EQU CYREG_BLE_BLELL_CONN_REQ_WORD2
BLE_cy_m0s8_ble__CONN_REQ_WORD3 EQU CYREG_BLE_BLELL_CONN_REQ_WORD3
BLE_cy_m0s8_ble__CONN_REQ_WORD4 EQU CYREG_BLE_BLELL_CONN_REQ_WORD4
BLE_cy_m0s8_ble__CONN_REQ_WORD5 EQU CYREG_BLE_BLELL_CONN_REQ_WORD5
BLE_cy_m0s8_ble__CONN_REQ_WORD6 EQU CYREG_BLE_BLELL_CONN_REQ_WORD6
BLE_cy_m0s8_ble__CONN_REQ_WORD7 EQU CYREG_BLE_BLELL_CONN_REQ_WORD7
BLE_cy_m0s8_ble__CONN_REQ_WORD8 EQU CYREG_BLE_BLELL_CONN_REQ_WORD8
BLE_cy_m0s8_ble__CONN_REQ_WORD9 EQU CYREG_BLE_BLELL_CONN_REQ_WORD9
BLE_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR EQU CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR
BLE_cy_m0s8_ble__CONN_STATUS EQU CYREG_BLE_BLELL_CONN_STATUS
BLE_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR EQU CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR
BLE_cy_m0s8_ble__CONN_UPDATE_NEW_INTERVAL EQU CYREG_BLE_BLELL_CONN_UPDATE_NEW_INTERVAL
BLE_cy_m0s8_ble__CONN_UPDATE_NEW_LATENCY EQU CYREG_BLE_BLELL_CONN_UPDATE_NEW_LATENCY
BLE_cy_m0s8_ble__CONN_UPDATE_NEW_SL_INTERVAL EQU CYREG_BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL
BLE_cy_m0s8_ble__CONN_UPDATE_NEW_SUP_TO EQU CYREG_BLE_BLELL_CONN_UPDATE_NEW_SUP_TO
BLE_cy_m0s8_ble__CTR1 EQU CYREG_BLE_BLERD_CTR1
BLE_cy_m0s8_ble__DATA_CHANNELS_H0 EQU CYREG_BLE_BLELL_DATA_CHANNELS_H0
BLE_cy_m0s8_ble__DATA_CHANNELS_H1 EQU CYREG_BLE_BLELL_DATA_CHANNELS_H1
BLE_cy_m0s8_ble__DATA_CHANNELS_L0 EQU CYREG_BLE_BLELL_DATA_CHANNELS_L0
BLE_cy_m0s8_ble__DATA_CHANNELS_L1 EQU CYREG_BLE_BLELL_DATA_CHANNELS_L1
BLE_cy_m0s8_ble__DATA_CHANNELS_M0 EQU CYREG_BLE_BLELL_DATA_CHANNELS_M0
BLE_cy_m0s8_ble__DATA_CHANNELS_M1 EQU CYREG_BLE_BLELL_DATA_CHANNELS_M1
BLE_cy_m0s8_ble__DATA_LIST_ACK_UPDATE__STATUS EQU CYREG_BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS
BLE_cy_m0s8_ble__DATA_LIST_SENT_UPDATE__STATUS EQU CYREG_BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS
BLE_cy_m0s8_ble__DATA_MEM_DESCRIPTOR0 EQU CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR0
BLE_cy_m0s8_ble__DATA_MEM_DESCRIPTOR1 EQU CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR1
BLE_cy_m0s8_ble__DATA_MEM_DESCRIPTOR2 EQU CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR2
BLE_cy_m0s8_ble__DATA_MEM_DESCRIPTOR3 EQU CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR3
BLE_cy_m0s8_ble__DATA_MEM_DESCRIPTOR4 EQU CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR4
BLE_cy_m0s8_ble__DATA0 EQU CYREG_BLE_BLELL_DATA0
BLE_cy_m0s8_ble__DATA1 EQU CYREG_BLE_BLELL_DATA1
BLE_cy_m0s8_ble__DATA10 EQU CYREG_BLE_BLELL_DATA10
BLE_cy_m0s8_ble__DATA11 EQU CYREG_BLE_BLELL_DATA11
BLE_cy_m0s8_ble__DATA12 EQU CYREG_BLE_BLELL_DATA12
BLE_cy_m0s8_ble__DATA13 EQU CYREG_BLE_BLELL_DATA13
BLE_cy_m0s8_ble__DATA2 EQU CYREG_BLE_BLELL_DATA2
BLE_cy_m0s8_ble__DATA3 EQU CYREG_BLE_BLELL_DATA3
BLE_cy_m0s8_ble__DATA4 EQU CYREG_BLE_BLELL_DATA4
BLE_cy_m0s8_ble__DATA5 EQU CYREG_BLE_BLELL_DATA5
BLE_cy_m0s8_ble__DATA6 EQU CYREG_BLE_BLELL_DATA6
BLE_cy_m0s8_ble__DATA7 EQU CYREG_BLE_BLELL_DATA7
BLE_cy_m0s8_ble__DATA8 EQU CYREG_BLE_BLELL_DATA8
BLE_cy_m0s8_ble__DATA9 EQU CYREG_BLE_BLELL_DATA9
BLE_cy_m0s8_ble__DBG_1 EQU CYREG_BLE_BLERD_DBG_1
BLE_cy_m0s8_ble__DBG_2 EQU CYREG_BLE_BLERD_DBG_2
BLE_cy_m0s8_ble__DBG_3 EQU CYREG_BLE_BLERD_DBG_3
BLE_cy_m0s8_ble__DBG_BB EQU CYREG_BLE_BLERD_DBG_BB
BLE_cy_m0s8_ble__DBUS EQU CYREG_BLE_BLERD_DBUS
BLE_cy_m0s8_ble__DC EQU CYREG_BLE_BLERD_DC
BLE_cy_m0s8_ble__DCCAL EQU CYREG_BLE_BLERD_DCCAL
BLE_cy_m0s8_ble__DEV_PUB_ADDR_H EQU CYREG_BLE_BLELL_DEV_PUB_ADDR_H
BLE_cy_m0s8_ble__DEV_PUB_ADDR_L EQU CYREG_BLE_BLELL_DEV_PUB_ADDR_L
BLE_cy_m0s8_ble__DEV_PUB_ADDR_M EQU CYREG_BLE_BLELL_DEV_PUB_ADDR_M
BLE_cy_m0s8_ble__DEVICE_RAND_ADDR_H EQU CYREG_BLE_BLELL_DEVICE_RAND_ADDR_H
BLE_cy_m0s8_ble__DEVICE_RAND_ADDR_L EQU CYREG_BLE_BLELL_DEVICE_RAND_ADDR_L
BLE_cy_m0s8_ble__DEVICE_RAND_ADDR_M EQU CYREG_BLE_BLELL_DEVICE_RAND_ADDR_M
BLE_cy_m0s8_ble__DIAG1 EQU CYREG_BLE_BLERD_DIAG1
BLE_cy_m0s8_ble__DPLL_CONFIG EQU CYREG_BLE_BLELL_DPLL_CONFIG
BLE_cy_m0s8_ble__DSM1 EQU CYREG_BLE_BLERD_DSM1
BLE_cy_m0s8_ble__DSM2 EQU CYREG_BLE_BLERD_DSM2
BLE_cy_m0s8_ble__DSM3 EQU CYREG_BLE_BLERD_DSM3
BLE_cy_m0s8_ble__DSM4 EQU CYREG_BLE_BLERD_DSM4
BLE_cy_m0s8_ble__DSM5 EQU CYREG_BLE_BLERD_DSM5
BLE_cy_m0s8_ble__DSM6 EQU CYREG_BLE_BLERD_DSM6
BLE_cy_m0s8_ble__DTM_RX_PKT_COUNT EQU CYREG_BLE_BLELL_DTM_RX_PKT_COUNT
BLE_cy_m0s8_ble__ENC_CONFIG EQU CYREG_BLE_BLELL_ENC_CONFIG
BLE_cy_m0s8_ble__ENC_INTR EQU CYREG_BLE_BLELL_ENC_INTR
BLE_cy_m0s8_ble__ENC_INTR_EN EQU CYREG_BLE_BLELL_ENC_INTR_EN
BLE_cy_m0s8_ble__ENC_KEY0 EQU CYREG_BLE_BLELL_ENC_KEY0
BLE_cy_m0s8_ble__ENC_KEY1 EQU CYREG_BLE_BLELL_ENC_KEY1
BLE_cy_m0s8_ble__ENC_KEY2 EQU CYREG_BLE_BLELL_ENC_KEY2
BLE_cy_m0s8_ble__ENC_KEY3 EQU CYREG_BLE_BLELL_ENC_KEY3
BLE_cy_m0s8_ble__ENC_KEY4 EQU CYREG_BLE_BLELL_ENC_KEY4
BLE_cy_m0s8_ble__ENC_KEY5 EQU CYREG_BLE_BLELL_ENC_KEY5
BLE_cy_m0s8_ble__ENC_KEY6 EQU CYREG_BLE_BLELL_ENC_KEY6
BLE_cy_m0s8_ble__ENC_KEY7 EQU CYREG_BLE_BLELL_ENC_KEY7
BLE_cy_m0s8_ble__ENC_PARAMS EQU CYREG_BLE_BLELL_ENC_PARAMS
BLE_cy_m0s8_ble__EVENT_ENABLE EQU CYREG_BLE_BLELL_EVENT_ENABLE
BLE_cy_m0s8_ble__EVENT_INTR EQU CYREG_BLE_BLELL_EVENT_INTR
BLE_cy_m0s8_ble__FCAL_TEST EQU CYREG_BLE_BLERD_FCAL_TEST
BLE_cy_m0s8_ble__FPD_TEST EQU CYREG_BLE_BLERD_FPD_TEST
BLE_cy_m0s8_ble__FSM EQU CYREG_BLE_BLERD_FSM
BLE_cy_m0s8_ble__IM EQU CYREG_BLE_BLERD_IM
BLE_cy_m0s8_ble__INIT_CONFIG EQU CYREG_BLE_BLELL_INIT_CONFIG
BLE_cy_m0s8_ble__INIT_INTERVAL EQU CYREG_BLE_BLELL_INIT_INTERVAL
BLE_cy_m0s8_ble__INIT_INTR EQU CYREG_BLE_BLELL_INIT_INTR
BLE_cy_m0s8_ble__INIT_NEXT_INSTANT EQU CYREG_BLE_BLELL_INIT_NEXT_INSTANT
BLE_cy_m0s8_ble__INIT_PARAM EQU CYREG_BLE_BLELL_INIT_PARAM
BLE_cy_m0s8_ble__INIT_SCN_ADV_RX_FIFO EQU CYREG_BLE_BLELL_INIT_SCN_ADV_RX_FIFO
BLE_cy_m0s8_ble__INIT_WINDOW EQU CYREG_BLE_BLELL_INIT_WINDOW
BLE_cy_m0s8_ble__IQMIS EQU CYREG_BLE_BLERD_IQMIS
BLE_cy_m0s8_ble__IV_MASTER0 EQU CYREG_BLE_BLELL_IV_MASTER0
BLE_cy_m0s8_ble__IV_MASTER1 EQU CYREG_BLE_BLELL_IV_MASTER1
BLE_cy_m0s8_ble__IV_SLAVE0 EQU CYREG_BLE_BLELL_IV_SLAVE0
BLE_cy_m0s8_ble__IV_SLAVE1 EQU CYREG_BLE_BLELL_IV_SLAVE1
BLE_cy_m0s8_ble__KVCAL EQU CYREG_BLE_BLERD_KVCAL
BLE_cy_m0s8_ble__LDO EQU CYREG_BLE_BLERD_LDO
BLE_cy_m0s8_ble__LDO_BYPASS EQU CYREG_BLE_BLERD_LDO_BYPASS
BLE_cy_m0s8_ble__LE_PING_TIMER_ADDR EQU CYREG_BLE_BLELL_LE_PING_TIMER_ADDR
BLE_cy_m0s8_ble__LE_PING_TIMER_NEXT_EXP EQU CYREG_BLE_BLELL_LE_PING_TIMER_NEXT_EXP
BLE_cy_m0s8_ble__LE_PING_TIMER_OFFSET EQU CYREG_BLE_BLELL_LE_PING_TIMER_OFFSET
BLE_cy_m0s8_ble__LE_PING_TIMER_WRAP_COUNT EQU CYREG_BLE_BLELL_LE_PING_TIMER_WRAP_COUNT
BLE_cy_m0s8_ble__LE_RF_TEST_MODE EQU CYREG_BLE_BLELL_LE_RF_TEST_MODE
BLE_cy_m0s8_ble__LF_CLK_CTRL EQU CYREG_BLE_BLESS_LF_CLK_CTRL
BLE_cy_m0s8_ble__LL_CLK_EN EQU CYREG_BLE_BLESS_LL_CLK_EN
BLE_cy_m0s8_ble__LL_DSM_CTRL EQU CYREG_BLE_BLESS_LL_DSM_CTRL
BLE_cy_m0s8_ble__LL_DSM_INTR_STAT EQU CYREG_BLE_BLESS_LL_DSM_INTR_STAT
BLE_cy_m0s8_ble__LLH_FEATURE_CONFIG EQU CYREG_BLE_BLELL_LLH_FEATURE_CONFIG
BLE_cy_m0s8_ble__MIC_IN0 EQU CYREG_BLE_BLELL_MIC_IN0
BLE_cy_m0s8_ble__MIC_IN1 EQU CYREG_BLE_BLELL_MIC_IN1
BLE_cy_m0s8_ble__MIC_OUT0 EQU CYREG_BLE_BLELL_MIC_OUT0
BLE_cy_m0s8_ble__MIC_OUT1 EQU CYREG_BLE_BLELL_MIC_OUT1
BLE_cy_m0s8_ble__MODEM EQU CYREG_BLE_BLERD_MODEM
BLE_cy_m0s8_ble__MONI EQU CYREG_BLE_BLERD_MONI
BLE_cy_m0s8_ble__NEXT_CE_INSTANT EQU CYREG_BLE_BLELL_NEXT_CE_INSTANT
BLE_cy_m0s8_ble__NEXT_RESP_TIMER_EXP EQU CYREG_BLE_BLELL_NEXT_RESP_TIMER_EXP
BLE_cy_m0s8_ble__NEXT_SUP_TO EQU CYREG_BLE_BLELL_NEXT_SUP_TO
BLE_cy_m0s8_ble__OFFSET_TO_FIRST_INSTANT EQU CYREG_BLE_BLELL_OFFSET_TO_FIRST_INSTANT
BLE_cy_m0s8_ble__PACKET_COUNTER0 EQU CYREG_BLE_BLELL_PACKET_COUNTER0
BLE_cy_m0s8_ble__PACKET_COUNTER1 EQU CYREG_BLE_BLELL_PACKET_COUNTER1
BLE_cy_m0s8_ble__PACKET_COUNTER2 EQU CYREG_BLE_BLELL_PACKET_COUNTER2
BLE_cy_m0s8_ble__PDU_ACCESS_ADDR_H_REGISTER EQU CYREG_BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER
BLE_cy_m0s8_ble__PDU_ACCESS_ADDR_L_REGISTER EQU CYREG_BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER
BLE_cy_m0s8_ble__PDU_RESP_TIMER EQU CYREG_BLE_BLELL_PDU_RESP_TIMER
BLE_cy_m0s8_ble__PEER_ADDR_H EQU CYREG_BLE_BLELL_PEER_ADDR_H
BLE_cy_m0s8_ble__PEER_ADDR_L EQU CYREG_BLE_BLELL_PEER_ADDR_L
BLE_cy_m0s8_ble__PEER_ADDR_M EQU CYREG_BLE_BLELL_PEER_ADDR_M
BLE_cy_m0s8_ble__POC_REG__TIM_CONTROL EQU CYREG_BLE_BLELL_POC_REG__TIM_CONTROL
BLE_cy_m0s8_ble__RCCAL EQU CYREG_BLE_BLERD_RCCAL
BLE_cy_m0s8_ble__READ_IQ_1 EQU CYREG_BLE_BLERD_READ_IQ_1
BLE_cy_m0s8_ble__READ_IQ_2 EQU CYREG_BLE_BLERD_READ_IQ_2
BLE_cy_m0s8_ble__READ_IQ_3 EQU CYREG_BLE_BLERD_READ_IQ_3
BLE_cy_m0s8_ble__READ_IQ_4 EQU CYREG_BLE_BLERD_READ_IQ_4
BLE_cy_m0s8_ble__RECEIVE_TRIG_CTRL EQU CYREG_BLE_BLELL_RECEIVE_TRIG_CTRL
BLE_cy_m0s8_ble__RF_CONFIG EQU CYREG_BLE_BLESS_RF_CONFIG
BLE_cy_m0s8_ble__RMAP EQU CYREG_BLE_BLERD_RMAP
BLE_cy_m0s8_ble__RSSI EQU CYREG_BLE_BLERD_RSSI
BLE_cy_m0s8_ble__RX EQU CYREG_BLE_BLERD_RX
BLE_cy_m0s8_ble__RX_BUMP1 EQU CYREG_BLE_BLERD_RX_BUMP1
BLE_cy_m0s8_ble__RX_BUMP2 EQU CYREG_BLE_BLERD_RX_BUMP2
BLE_cy_m0s8_ble__SCAN_CONFIG EQU CYREG_BLE_BLELL_SCAN_CONFIG
BLE_cy_m0s8_ble__SCAN_INTERVAL EQU CYREG_BLE_BLELL_SCAN_INTERVAL
BLE_cy_m0s8_ble__SCAN_INTR EQU CYREG_BLE_BLELL_SCAN_INTR
BLE_cy_m0s8_ble__SCAN_NEXT_INSTANT EQU CYREG_BLE_BLELL_SCAN_NEXT_INSTANT
BLE_cy_m0s8_ble__SCAN_PARAM EQU CYREG_BLE_BLELL_SCAN_PARAM
BLE_cy_m0s8_ble__SCAN_WINDOW EQU CYREG_BLE_BLELL_SCAN_WINDOW
BLE_cy_m0s8_ble__SL_CONN_INTERVAL EQU CYREG_BLE_BLELL_SL_CONN_INTERVAL
BLE_cy_m0s8_ble__SLAVE_LATENCY EQU CYREG_BLE_BLELL_SLAVE_LATENCY
BLE_cy_m0s8_ble__SLAVE_TIMING_CONTROL EQU CYREG_BLE_BLELL_SLAVE_TIMING_CONTROL
BLE_cy_m0s8_ble__SLV_WIN_ADJ EQU CYREG_BLE_BLELL_SLV_WIN_ADJ
BLE_cy_m0s8_ble__SUP_TIMEOUT EQU CYREG_BLE_BLELL_SUP_TIMEOUT
BLE_cy_m0s8_ble__SY EQU CYREG_BLE_BLERD_SY
BLE_cy_m0s8_ble__SY_BUMP1 EQU CYREG_BLE_BLERD_SY_BUMP1
BLE_cy_m0s8_ble__SY_BUMP2 EQU CYREG_BLE_BLERD_SY_BUMP2
BLE_cy_m0s8_ble__TEST EQU CYREG_BLE_BLERD_TEST
BLE_cy_m0s8_ble__TEST2_SY EQU CYREG_BLE_BLERD_TEST2_SY
BLE_cy_m0s8_ble__THRSHD1 EQU CYREG_BLE_BLERD_THRSHD1
BLE_cy_m0s8_ble__THRSHD2 EQU CYREG_BLE_BLERD_THRSHD2
BLE_cy_m0s8_ble__THRSHD3 EQU CYREG_BLE_BLERD_THRSHD3
BLE_cy_m0s8_ble__THRSHD4 EQU CYREG_BLE_BLERD_THRSHD4
BLE_cy_m0s8_ble__THRSHD5 EQU CYREG_BLE_BLERD_THRSHD5
BLE_cy_m0s8_ble__TIM_COUNTER_L EQU CYREG_BLE_BLELL_TIM_COUNTER_L
BLE_cy_m0s8_ble__TRANSMIT_WINDOW_OFFSET EQU CYREG_BLE_BLELL_TRANSMIT_WINDOW_OFFSET
BLE_cy_m0s8_ble__TRANSMIT_WINDOW_SIZE EQU CYREG_BLE_BLELL_TRANSMIT_WINDOW_SIZE
BLE_cy_m0s8_ble__TX EQU CYREG_BLE_BLERD_TX
BLE_cy_m0s8_ble__TX_BUMP1 EQU CYREG_BLE_BLERD_TX_BUMP1
BLE_cy_m0s8_ble__TX_BUMP2 EQU CYREG_BLE_BLERD_TX_BUMP2
BLE_cy_m0s8_ble__TX_EN_EXT_DELAY EQU CYREG_BLE_BLELL_TX_EN_EXT_DELAY
BLE_cy_m0s8_ble__TX_RX_ON_DELAY EQU CYREG_BLE_BLELL_TX_RX_ON_DELAY
BLE_cy_m0s8_ble__TX_RX_SYNTH_DELAY EQU CYREG_BLE_BLELL_TX_RX_SYNTH_DELAY
BLE_cy_m0s8_ble__TXRX_HOP EQU CYREG_BLE_BLELL_TXRX_HOP
BLE_cy_m0s8_ble__WAKEUP_CONFIG EQU CYREG_BLE_BLELL_WAKEUP_CONFIG
BLE_cy_m0s8_ble__WAKEUP_CONTROL EQU CYREG_BLE_BLELL_WAKEUP_CONTROL
BLE_cy_m0s8_ble__WCO_CONFIG EQU CYREG_BLE_BLESS_WCO_CONFIG
BLE_cy_m0s8_ble__WCO_STATUS EQU CYREG_BLE_BLESS_WCO_STATUS
BLE_cy_m0s8_ble__WCO_TRIM EQU CYREG_BLE_BLESS_WCO_TRIM
BLE_cy_m0s8_ble__WHITELIST_BASE_ADDR EQU CYREG_BLE_BLELL_WHITELIST_BASE_ADDR
BLE_cy_m0s8_ble__WIN_MIN_STEP_SIZE EQU CYREG_BLE_BLELL_WIN_MIN_STEP_SIZE
BLE_cy_m0s8_ble__WINDOW_WIDEN_INTVL EQU CYREG_BLE_BLELL_WINDOW_WIDEN_INTVL
BLE_cy_m0s8_ble__WINDOW_WIDEN_WINOFF EQU CYREG_BLE_BLELL_WINDOW_WIDEN_WINOFF
BLE_cy_m0s8_ble__WL_ADDR_TYPE EQU CYREG_BLE_BLELL_WL_ADDR_TYPE
BLE_cy_m0s8_ble__WL_ENABLE EQU CYREG_BLE_BLELL_WL_ENABLE
BLE_cy_m0s8_ble__XTAL_CLK_DIV_CONFIG EQU CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG

/* UART_rx */
UART_rx__0__DR EQU CYREG_GPIO_PRT1_DR
UART_rx__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_rx__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_rx__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_rx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
UART_rx__0__HSIOM_GPIO EQU 0
UART_rx__0__HSIOM_I2C EQU 14
UART_rx__0__HSIOM_I2C_SDA EQU 14
UART_rx__0__HSIOM_MASK EQU 0x000F0000
UART_rx__0__HSIOM_SHIFT EQU 16
UART_rx__0__HSIOM_SPI EQU 15
UART_rx__0__HSIOM_SPI_MOSI EQU 15
UART_rx__0__HSIOM_UART EQU 9
UART_rx__0__HSIOM_UART_RX EQU 9
UART_rx__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__0__INTR EQU CYREG_GPIO_PRT1_INTR
UART_rx__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_rx__0__MASK EQU 0x10
UART_rx__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
UART_rx__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
UART_rx__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
UART_rx__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
UART_rx__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
UART_rx__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
UART_rx__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
UART_rx__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
UART_rx__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
UART_rx__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
UART_rx__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
UART_rx__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
UART_rx__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
UART_rx__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
UART_rx__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
UART_rx__0__PC EQU CYREG_GPIO_PRT1_PC
UART_rx__0__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_rx__0__PORT EQU 1
UART_rx__0__PS EQU CYREG_GPIO_PRT1_PS
UART_rx__0__SHIFT EQU 4
UART_rx__DR EQU CYREG_GPIO_PRT1_DR
UART_rx__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_rx__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_rx__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_rx__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__INTR EQU CYREG_GPIO_PRT1_INTR
UART_rx__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_rx__MASK EQU 0x10
UART_rx__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
UART_rx__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
UART_rx__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
UART_rx__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
UART_rx__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
UART_rx__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
UART_rx__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
UART_rx__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
UART_rx__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
UART_rx__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
UART_rx__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
UART_rx__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
UART_rx__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
UART_rx__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
UART_rx__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
UART_rx__PC EQU CYREG_GPIO_PRT1_PC
UART_rx__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_rx__PORT EQU 1
UART_rx__PS EQU CYREG_GPIO_PRT1_PS
UART_rx__SHIFT EQU 4

/* UART_SCB */
UART_SCB__CTRL EQU CYREG_SCB0_CTRL
UART_SCB__EZ_DATA0 EQU CYREG_SCB0_EZ_DATA0
UART_SCB__EZ_DATA1 EQU CYREG_SCB0_EZ_DATA1
UART_SCB__EZ_DATA10 EQU CYREG_SCB0_EZ_DATA10
UART_SCB__EZ_DATA11 EQU CYREG_SCB0_EZ_DATA11
UART_SCB__EZ_DATA12 EQU CYREG_SCB0_EZ_DATA12
UART_SCB__EZ_DATA13 EQU CYREG_SCB0_EZ_DATA13
UART_SCB__EZ_DATA14 EQU CYREG_SCB0_EZ_DATA14
UART_SCB__EZ_DATA15 EQU CYREG_SCB0_EZ_DATA15
UART_SCB__EZ_DATA16 EQU CYREG_SCB0_EZ_DATA16
UART_SCB__EZ_DATA17 EQU CYREG_SCB0_EZ_DATA17
UART_SCB__EZ_DATA18 EQU CYREG_SCB0_EZ_DATA18
UART_SCB__EZ_DATA19 EQU CYREG_SCB0_EZ_DATA19
UART_SCB__EZ_DATA2 EQU CYREG_SCB0_EZ_DATA2
UART_SCB__EZ_DATA20 EQU CYREG_SCB0_EZ_DATA20
UART_SCB__EZ_DATA21 EQU CYREG_SCB0_EZ_DATA21
UART_SCB__EZ_DATA22 EQU CYREG_SCB0_EZ_DATA22
UART_SCB__EZ_DATA23 EQU CYREG_SCB0_EZ_DATA23
UART_SCB__EZ_DATA24 EQU CYREG_SCB0_EZ_DATA24
UART_SCB__EZ_DATA25 EQU CYREG_SCB0_EZ_DATA25
UART_SCB__EZ_DATA26 EQU CYREG_SCB0_EZ_DATA26
UART_SCB__EZ_DATA27 EQU CYREG_SCB0_EZ_DATA27
UART_SCB__EZ_DATA28 EQU CYREG_SCB0_EZ_DATA28
UART_SCB__EZ_DATA29 EQU CYREG_SCB0_EZ_DATA29
UART_SCB__EZ_DATA3 EQU CYREG_SCB0_EZ_DATA3
UART_SCB__EZ_DATA30 EQU CYREG_SCB0_EZ_DATA30
UART_SCB__EZ_DATA31 EQU CYREG_SCB0_EZ_DATA31
UART_SCB__EZ_DATA4 EQU CYREG_SCB0_EZ_DATA4
UART_SCB__EZ_DATA5 EQU CYREG_SCB0_EZ_DATA5
UART_SCB__EZ_DATA6 EQU CYREG_SCB0_EZ_DATA6
UART_SCB__EZ_DATA7 EQU CYREG_SCB0_EZ_DATA7
UART_SCB__EZ_DATA8 EQU CYREG_SCB0_EZ_DATA8
UART_SCB__EZ_DATA9 EQU CYREG_SCB0_EZ_DATA9
UART_SCB__I2C_CFG EQU CYREG_SCB0_I2C_CFG
UART_SCB__I2C_CTRL EQU CYREG_SCB0_I2C_CTRL
UART_SCB__I2C_M_CMD EQU CYREG_SCB0_I2C_M_CMD
UART_SCB__I2C_S_CMD EQU CYREG_SCB0_I2C_S_CMD
UART_SCB__I2C_STATUS EQU CYREG_SCB0_I2C_STATUS
UART_SCB__INTR_CAUSE EQU CYREG_SCB0_INTR_CAUSE
UART_SCB__INTR_I2C_EC EQU CYREG_SCB0_INTR_I2C_EC
UART_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB0_INTR_I2C_EC_MASK
UART_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB0_INTR_I2C_EC_MASKED
UART_SCB__INTR_M EQU CYREG_SCB0_INTR_M
UART_SCB__INTR_M_MASK EQU CYREG_SCB0_INTR_M_MASK
UART_SCB__INTR_M_MASKED EQU CYREG_SCB0_INTR_M_MASKED
UART_SCB__INTR_M_SET EQU CYREG_SCB0_INTR_M_SET
UART_SCB__INTR_RX EQU CYREG_SCB0_INTR_RX
UART_SCB__INTR_RX_MASK EQU CYREG_SCB0_INTR_RX_MASK
UART_SCB__INTR_RX_MASKED EQU CYREG_SCB0_INTR_RX_MASKED
UART_SCB__INTR_RX_SET EQU CYREG_SCB0_INTR_RX_SET
UART_SCB__INTR_S EQU CYREG_SCB0_INTR_S
UART_SCB__INTR_S_MASK EQU CYREG_SCB0_INTR_S_MASK
UART_SCB__INTR_S_MASKED EQU CYREG_SCB0_INTR_S_MASKED
UART_SCB__INTR_S_SET EQU CYREG_SCB0_INTR_S_SET
UART_SCB__INTR_SPI_EC EQU CYREG_SCB0_INTR_SPI_EC
UART_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB0_INTR_SPI_EC_MASK
UART_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB0_INTR_SPI_EC_MASKED
UART_SCB__INTR_TX EQU CYREG_SCB0_INTR_TX
UART_SCB__INTR_TX_MASK EQU CYREG_SCB0_INTR_TX_MASK
UART_SCB__INTR_TX_MASKED EQU CYREG_SCB0_INTR_TX_MASKED
UART_SCB__INTR_TX_SET EQU CYREG_SCB0_INTR_TX_SET
UART_SCB__RX_CTRL EQU CYREG_SCB0_RX_CTRL
UART_SCB__RX_FIFO_CTRL EQU CYREG_SCB0_RX_FIFO_CTRL
UART_SCB__RX_FIFO_RD EQU CYREG_SCB0_RX_FIFO_RD
UART_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB0_RX_FIFO_RD_SILENT
UART_SCB__RX_FIFO_STATUS EQU CYREG_SCB0_RX_FIFO_STATUS
UART_SCB__RX_MATCH EQU CYREG_SCB0_RX_MATCH
UART_SCB__SPI_CTRL EQU CYREG_SCB0_SPI_CTRL
UART_SCB__SPI_STATUS EQU CYREG_SCB0_SPI_STATUS
UART_SCB__SS0_POSISTION EQU 0
UART_SCB__SS1_POSISTION EQU 1
UART_SCB__SS2_POSISTION EQU 2
UART_SCB__SS3_POSISTION EQU 3
UART_SCB__STATUS EQU CYREG_SCB0_STATUS
UART_SCB__TX_CTRL EQU CYREG_SCB0_TX_CTRL
UART_SCB__TX_FIFO_CTRL EQU CYREG_SCB0_TX_FIFO_CTRL
UART_SCB__TX_FIFO_STATUS EQU CYREG_SCB0_TX_FIFO_STATUS
UART_SCB__TX_FIFO_WR EQU CYREG_SCB0_TX_FIFO_WR
UART_SCB__UART_CTRL EQU CYREG_SCB0_UART_CTRL
UART_SCB__UART_FLOW_CTRL EQU CYREG_SCB0_UART_FLOW_CTRL
UART_SCB__UART_RX_CTRL EQU CYREG_SCB0_UART_RX_CTRL
UART_SCB__UART_RX_STATUS EQU CYREG_SCB0_UART_RX_STATUS
UART_SCB__UART_TX_CTRL EQU CYREG_SCB0_UART_TX_CTRL

/* UART_SCB_IRQ */
UART_SCB_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
UART_SCB_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
UART_SCB_IRQ__INTC_MASK EQU 0x200
UART_SCB_IRQ__INTC_NUMBER EQU 9
UART_SCB_IRQ__INTC_PRIOR_MASK EQU 0xC000
UART_SCB_IRQ__INTC_PRIOR_NUM EQU 3
UART_SCB_IRQ__INTC_PRIOR_REG EQU CYREG_CM0_IPR2
UART_SCB_IRQ__INTC_SET_EN_REG EQU CYREG_CM0_ISER
UART_SCB_IRQ__INTC_SET_PD_REG EQU CYREG_CM0_ISPR

/* UART_SCBCLK */
UART_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL1
UART_SCBCLK__DIV_ID EQU 0x00000040
UART_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL0
UART_SCBCLK__PA_DIV_ID EQU 0x000000FF

/* UART_tx */
UART_tx__0__DR EQU CYREG_GPIO_PRT1_DR
UART_tx__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_tx__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_tx__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
UART_tx__0__HSIOM_GPIO EQU 0
UART_tx__0__HSIOM_I2C EQU 14
UART_tx__0__HSIOM_I2C_SCL EQU 14
UART_tx__0__HSIOM_MASK EQU 0x00F00000
UART_tx__0__HSIOM_SHIFT EQU 20
UART_tx__0__HSIOM_SPI EQU 15
UART_tx__0__HSIOM_SPI_MISO EQU 15
UART_tx__0__HSIOM_UART EQU 9
UART_tx__0__HSIOM_UART_TX EQU 9
UART_tx__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__0__INTR EQU CYREG_GPIO_PRT1_INTR
UART_tx__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_tx__0__MASK EQU 0x20
UART_tx__0__OUT_SEL EQU CYREG_UDB_PA1_CFG10
UART_tx__0__OUT_SEL_SHIFT EQU 10
UART_tx__0__OUT_SEL_VAL EQU -1
UART_tx__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
UART_tx__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
UART_tx__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
UART_tx__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
UART_tx__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
UART_tx__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
UART_tx__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
UART_tx__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
UART_tx__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
UART_tx__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
UART_tx__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
UART_tx__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
UART_tx__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
UART_tx__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
UART_tx__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
UART_tx__0__PC EQU CYREG_GPIO_PRT1_PC
UART_tx__0__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_tx__0__PORT EQU 1
UART_tx__0__PS EQU CYREG_GPIO_PRT1_PS
UART_tx__0__SHIFT EQU 5
UART_tx__DR EQU CYREG_GPIO_PRT1_DR
UART_tx__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_tx__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_tx__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_tx__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__INTR EQU CYREG_GPIO_PRT1_INTR
UART_tx__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_tx__MASK EQU 0x20
UART_tx__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
UART_tx__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
UART_tx__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
UART_tx__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
UART_tx__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
UART_tx__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
UART_tx__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
UART_tx__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
UART_tx__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
UART_tx__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
UART_tx__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
UART_tx__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
UART_tx__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
UART_tx__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
UART_tx__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
UART_tx__PC EQU CYREG_GPIO_PRT1_PC
UART_tx__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_tx__PORT EQU 1
UART_tx__PS EQU CYREG_GPIO_PRT1_PS
UART_tx__SHIFT EQU 5

/* Pin_CMD */
Pin_CMD__0__DR EQU CYREG_GPIO_PRT2_DR
Pin_CMD__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_CMD__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_CMD__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_CMD__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_CMD__0__HSIOM_MASK EQU 0x0F000000
Pin_CMD__0__HSIOM_SHIFT EQU 24
Pin_CMD__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_CMD__0__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_CMD__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_CMD__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_CMD__0__MASK EQU 0x40
Pin_CMD__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_CMD__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_CMD__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_CMD__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_CMD__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_CMD__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_CMD__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_CMD__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_CMD__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_CMD__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_CMD__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_CMD__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_CMD__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_CMD__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_CMD__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_CMD__0__PC EQU CYREG_GPIO_PRT2_PC
Pin_CMD__0__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_CMD__0__PORT EQU 2
Pin_CMD__0__PS EQU CYREG_GPIO_PRT2_PS
Pin_CMD__0__SHIFT EQU 6
Pin_CMD__DR EQU CYREG_GPIO_PRT2_DR
Pin_CMD__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_CMD__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_CMD__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_CMD__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_CMD__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_CMD__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_CMD__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_CMD__MASK EQU 0x40
Pin_CMD__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
Pin_CMD__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
Pin_CMD__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
Pin_CMD__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
Pin_CMD__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
Pin_CMD__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
Pin_CMD__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
Pin_CMD__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
Pin_CMD__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
Pin_CMD__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
Pin_CMD__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
Pin_CMD__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
Pin_CMD__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
Pin_CMD__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
Pin_CMD__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
Pin_CMD__PC EQU CYREG_GPIO_PRT2_PC
Pin_CMD__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_CMD__PORT EQU 2
Pin_CMD__PS EQU CYREG_GPIO_PRT2_PS
Pin_CMD__SHIFT EQU 6

/* Conn_LED */
Conn_LED__0__DR EQU CYREG_GPIO_PRT3_DR
Conn_LED__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
Conn_LED__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
Conn_LED__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
Conn_LED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
Conn_LED__0__HSIOM_MASK EQU 0x0000F000
Conn_LED__0__HSIOM_SHIFT EQU 12
Conn_LED__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
Conn_LED__0__INTR EQU CYREG_GPIO_PRT3_INTR
Conn_LED__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
Conn_LED__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
Conn_LED__0__MASK EQU 0x08
Conn_LED__0__PA__CFG0 EQU CYREG_UDB_PA3_CFG0
Conn_LED__0__PA__CFG1 EQU CYREG_UDB_PA3_CFG1
Conn_LED__0__PA__CFG10 EQU CYREG_UDB_PA3_CFG10
Conn_LED__0__PA__CFG11 EQU CYREG_UDB_PA3_CFG11
Conn_LED__0__PA__CFG12 EQU CYREG_UDB_PA3_CFG12
Conn_LED__0__PA__CFG13 EQU CYREG_UDB_PA3_CFG13
Conn_LED__0__PA__CFG14 EQU CYREG_UDB_PA3_CFG14
Conn_LED__0__PA__CFG2 EQU CYREG_UDB_PA3_CFG2
Conn_LED__0__PA__CFG3 EQU CYREG_UDB_PA3_CFG3
Conn_LED__0__PA__CFG4 EQU CYREG_UDB_PA3_CFG4
Conn_LED__0__PA__CFG5 EQU CYREG_UDB_PA3_CFG5
Conn_LED__0__PA__CFG6 EQU CYREG_UDB_PA3_CFG6
Conn_LED__0__PA__CFG7 EQU CYREG_UDB_PA3_CFG7
Conn_LED__0__PA__CFG8 EQU CYREG_UDB_PA3_CFG8
Conn_LED__0__PA__CFG9 EQU CYREG_UDB_PA3_CFG9
Conn_LED__0__PC EQU CYREG_GPIO_PRT3_PC
Conn_LED__0__PC2 EQU CYREG_GPIO_PRT3_PC2
Conn_LED__0__PORT EQU 3
Conn_LED__0__PS EQU CYREG_GPIO_PRT3_PS
Conn_LED__0__SHIFT EQU 3
Conn_LED__DR EQU CYREG_GPIO_PRT3_DR
Conn_LED__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
Conn_LED__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
Conn_LED__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
Conn_LED__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
Conn_LED__INTR EQU CYREG_GPIO_PRT3_INTR
Conn_LED__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
Conn_LED__INTSTAT EQU CYREG_GPIO_PRT3_INTR
Conn_LED__MASK EQU 0x08
Conn_LED__PA__CFG0 EQU CYREG_UDB_PA3_CFG0
Conn_LED__PA__CFG1 EQU CYREG_UDB_PA3_CFG1
Conn_LED__PA__CFG10 EQU CYREG_UDB_PA3_CFG10
Conn_LED__PA__CFG11 EQU CYREG_UDB_PA3_CFG11
Conn_LED__PA__CFG12 EQU CYREG_UDB_PA3_CFG12
Conn_LED__PA__CFG13 EQU CYREG_UDB_PA3_CFG13
Conn_LED__PA__CFG14 EQU CYREG_UDB_PA3_CFG14
Conn_LED__PA__CFG2 EQU CYREG_UDB_PA3_CFG2
Conn_LED__PA__CFG3 EQU CYREG_UDB_PA3_CFG3
Conn_LED__PA__CFG4 EQU CYREG_UDB_PA3_CFG4
Conn_LED__PA__CFG5 EQU CYREG_UDB_PA3_CFG5
Conn_LED__PA__CFG6 EQU CYREG_UDB_PA3_CFG6
Conn_LED__PA__CFG7 EQU CYREG_UDB_PA3_CFG7
Conn_LED__PA__CFG8 EQU CYREG_UDB_PA3_CFG8
Conn_LED__PA__CFG9 EQU CYREG_UDB_PA3_CFG9
Conn_LED__PC EQU CYREG_GPIO_PRT3_PC
Conn_LED__PC2 EQU CYREG_GPIO_PRT3_PC2
Conn_LED__PORT EQU 3
Conn_LED__PS EQU CYREG_GPIO_PRT3_PS
Conn_LED__SHIFT EQU 3

/* Miscellaneous */
CYDEV_BCLK__HFCLK__HZ EQU 48000000
CYDEV_BCLK__HFCLK__KHZ EQU 48000
CYDEV_BCLK__HFCLK__MHZ EQU 48
CYDEV_BCLK__SYSCLK__HZ EQU 48000000
CYDEV_BCLK__SYSCLK__KHZ EQU 48000
CYDEV_BCLK__SYSCLK__MHZ EQU 48
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 19
CYDEV_CHIP_DIE_PSOC4A EQU 11
CYDEV_CHIP_DIE_PSOC5LP EQU 18
CYDEV_CHIP_DIE_TMA4 EQU 2
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4
CYDEV_CHIP_JTAG_ID EQU 0x0E09119E
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 11
CYDEV_CHIP_MEMBER_4C EQU 16
CYDEV_CHIP_MEMBER_4D EQU 7
CYDEV_CHIP_MEMBER_4E EQU 4
CYDEV_CHIP_MEMBER_4F EQU 12
CYDEV_CHIP_MEMBER_4G EQU 2
CYDEV_CHIP_MEMBER_4H EQU 10
CYDEV_CHIP_MEMBER_4I EQU 15
CYDEV_CHIP_MEMBER_4J EQU 8
CYDEV_CHIP_MEMBER_4K EQU 9
CYDEV_CHIP_MEMBER_4L EQU 14
CYDEV_CHIP_MEMBER_4M EQU 13
CYDEV_CHIP_MEMBER_4N EQU 6
CYDEV_CHIP_MEMBER_4O EQU 5
CYDEV_CHIP_MEMBER_4U EQU 3
CYDEV_CHIP_MEMBER_5A EQU 18
CYDEV_CHIP_MEMBER_5B EQU 17
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4F
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4F_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_READ_ACCELERATOR EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_PROTECT_KILL EQU 4
CYDEV_DEBUG_PROTECT_OPEN EQU 1
CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN
CYDEV_DEBUG_PROTECT_PROTECTED EQU 2
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DFT_SELECT_CLK0 EQU 10
CYDEV_DFT_SELECT_CLK1 EQU 11
CYDEV_HEAP_SIZE EQU 0x80
CYDEV_IMO_TRIMMED_BY_USB EQU 0
CYDEV_IMO_TRIMMED_BY_WCO EQU 0
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_STACK_SIZE EQU 0x0800
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 1
CYDEV_VDDA_MV EQU 3300
CYDEV_VDDD_MV EQU 3300
CYDEV_VDDR_MV EQU 3300
CYDEV_WDT_GENERATE_ISR EQU 0
CYIPBLOCK_m0s8bless_VERSION EQU 1
CYIPBLOCK_m0s8cpussv2_VERSION EQU 1
CYIPBLOCK_m0s8csd_VERSION EQU 1
CYIPBLOCK_m0s8ioss_VERSION EQU 1
CYIPBLOCK_m0s8lcd_VERSION EQU 2
CYIPBLOCK_m0s8peri_VERSION EQU 1
CYIPBLOCK_m0s8scb_VERSION EQU 2
CYIPBLOCK_m0s8srssv2_VERSION EQU 1
CYIPBLOCK_m0s8tcpwm_VERSION EQU 2
CYIPBLOCK_m0s8udbif_VERSION EQU 1
CYIPBLOCK_s8pass4al_VERSION EQU 1
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERIAR_INC */
